Double-implanted GaAs complementary JFET's

1 January 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 5 (1), 21-23
https://doi.org/10.1109/edl.1984.25817

Abstract

The fabrication and performance characteristics of double-implanted GaAs complementary junction field-effect transistors (JFET's) suitable for low-power digital integrated circuit applications are described. Effective mobilities for the n-channel enhancement-mode JFET are 3500 cm²/V.s and for the p-channel 300 cm²/V.s. Experimental results of an ultra-low-power static RAM are presented.

Keywords

This publication has 6 references indexed in Scilit:

IVA-4 an ultra-low power, high speed GaAs 256-bit static RAM with depletion mode MESFETs
IEEE Transactions on Electron Devices, 1983
LSI processing technology for planar GaAs integrated circuits
IEEE Transactions on Electron Devices, 1980
Analysis of GaAs FET's for integrated logic
IEEE Transactions on Electron Devices, 1980
Fully ion implanted planar GaAs E-JFET process
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1979
Femtojoule high speed planar GaAs E-JFET logic
IEEE Transactions on Electron Devices, 1978
Properties of p-Type GaAs Prepared by Copper Diffusion
Journal of Applied Physics, 1960

Cited by 31 articles