Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
Top Cited Papers
- 6 May 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 17 references indexed in Scilit:
- Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scalingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Confidence estimation for speculation controlPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 600 MHz superscalar RISC microprocessor with out-of-order executionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Automatically characterizing large scale program behaviorPublished by Association for Computing Machinery (ACM) ,2002
- Unified architecture level energy-efficiency metricPublished by Association for Computing Machinery (ACM) ,2002
- The simulation and evaluation of dynamic voltage scaling algorithmsPublished by Association for Computing Machinery (ACM) ,1998
- Comparing algorithm for dynamic speed-setting of a low-power CPUPublished by Association for Computing Machinery (ACM) ,1995
- A 200-MHz 64-b dual-issue CMOS microprocessorIEEE Journal of Solid-State Circuits, 1992
- An area model for on-chip memories and its applicationIEEE Journal of Solid-State Circuits, 1991
- Limits of instruction-level parallelismPublished by Association for Computing Machinery (ACM) ,1991