A broadband frequency doubler that uses distributed amplifier techniques has been designed to operate over several octaves of bandwidth. The circuit design suppresses the fundamental frequency energy present at the output port while maximizing the second harmonic signal. The design can be realized using monolithic or conventional microwave circuit techniques for use in local oscillator chains. To demonstrate the multiplier concept, a two-cell monolithic circuit was designed. The doubler is composed of four FETs with gate widths of 176 mu m. The completed frequency doubler chip was used in the design of a 5-9-GHz (10-8-GHz output frequency) multiplier chain. The chain used several stages of post- and preamplification to set input drive levels and to provide increased local oscillator power. A 9-dB variation in input power produces only 3 dB of output power variation. With the chain fully driven, the total power output variation is less than +or-1 dB. The multipliers exhibit excellent power output characteristics, with fundamental frequency suppression, and require no tuning.