Digital Logic Simulation in a Time-Based, Table-Driven Environment
- 1 March 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 8 (3), 38-49
- https://doi.org/10.1109/C-M.1975.218900
Abstract
Digital simulation is the process of modeling, by computer programs, the behavior of a digital network. Digital fault simulation is the modeling of a digital network in the presence of a physical defect. The term "fault" is used to refer to some representation of a physical defect. A simple example of this is the case where an input connection to an AND gate is broken. This would be referred to as a stuck-at-1 fault. Hence the phrase fault simulation.Keywords
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