A Nand Model ror Fault Diagnosis in Combinational Logic Networks
- 1 December 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-20 (12), 1496-1506
- https://doi.org/10.1109/t-c.1971.223162
Abstract
A network model colled the normal NAND model is introduced for the study of fault diagnosis in combinational logic circuits. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained. The use of this model greatly simplifies fault analysis and test generation.Keywords
This publication has 6 references indexed in Scilit:
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