Generation of Hazard Free Tests Using the D-Algorithm in a Timing Accurate System for Logic and Deductive Fault Simulation
- 1 January 1979
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
It is described how a timing accurate system for logic and deductive fault simulation can be used in the forward tracing part of the D-algorithm. The logic simulation is used for the forward implication and the verification phases. The deductive fault simulator is used for D-propagation. Some results from executions of the test generation program are presented.Keywords
This publication has 5 references indexed in Scilit:
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976
- Comparison of Parallel and Deductive Fault Simulation MethodsIEEE Transactions on Computers, 1974
- Procedures for Eliminating Static and Dynamic Hazards in Test GenerationIEEE Transactions on Computers, 1974
- A Deductive Method for Simulating Faults in Logic CircuitsIEEE Transactions on Computers, 1972
- Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic CircuitsIEEE Transactions on Electronic Computers, 1967