Multiple-Read Single-Write Memory and Its Applications

Abstract

A multiple-read single-write (MRSW) memory is proposed as a hardware solution to the memory and bus conflict problem in distributed and multiprocessing computing systems. Each memory module is assigned to a host processor which is hardwired to its read–write channel. Its read-only channels are shared by a few closely coupled processors, I/O devices, and/or a data bus which provides access to all other processors. The exact processor-memory organization is determined by a module correlation criteria, which also yields a quantitative measure of the effectiveness of the solution. In a class of scientific computing problems where module correlation is limited to neighboring modules, the memory conflict problem is completely eliminated. The processors may operate as array processors controlled by a CPU, or they may operate autonomously with capabilities of originating programs or transactions. The location conflict problem of multiaccess memories is resolved without additional hardware or delay.