Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network

Abstract

Banyan networks are being proposed for interconnecting memory and processor modules in multiprocessor systems as well as for packet switching in communication networks. This paper describes an analysis of the performance of a packet switch based on a single-buffered Banyan network. A model of a single-buffered Banyan network provides results on the throughput, delay, and internal blocking. Results of this model are combined with models of the buffer controller (finite and infinite buffers). It is shown that for balanced loads, the switching delay is low for loads below maximum throughput (about 45 percent per input link) and the blocking at the input buffer controller is low for reasonable buffer sizes.