Suppression of latch in SOI MOSFETs by silicidation of source

Abstract

It is demonstrated that silicidation of the source region in a silicon-on-insulator MOSFET can improve the parasitic bipolar induced breakdown voltage to beyond 5 V. The technique results in a degradation of the parasitic bipolar current gain by increasing the minority carrier current across the source body junction, thereby causing a reduction in the emitter efficiency. Silicidation of both the source and drain regions is performed simultaneously thus maintaining device symmetry and simplicity of processing. No significant degradation of drain leakage leakage current was observed.