Queueing analysis for ATM switching of mixed continuous-bit-rate and bursty traffic
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Mixed continuous-bit-rate (CBR) and bursty traffic contending for transmission on any output line of a broadband switch based on the asynchronous transfer mode (ATM) is modeled as a superposition of traffic from a number of independent random and binary sources. With the use of a recursive algorithm, a complete queuing analysis is presented. The queue length distribution, the delay distribution, and the cell loss probability for a finite buffer system are exactly calculated. Cases considered and analyzed include: delay priority for CBR traffic, absolute cell loss priority for DS1/DS3 emulation or guaranteed bandwidth CBR traffic with a stringent cell loss requirement, and threshold cell dropping for voice CBR traffic with a high degree of cell loss tolerance Author(s) Ting-Chao Hou AT&T Bell Lab., Holmdel, NJ, USA Wong, A.K.Keywords
This publication has 9 references indexed in Scilit:
- Output-buffer switch architecture for asynchronous transfer modePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A shared buffer memory switch for an ATM exchangePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Effects of output buffer sharing on buffer requirements in an ATDM packet switchingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Using a packet switch for circuit-switched traffic: a queueing system with periodic input trafficIEEE Transactions on Communications, 1989
- Buffer sizing for synchronous self‐routeing broadband packet switches with bursty trafficInternational Journal of Communication Systems, 1989
- Input Versus Output Queueing on a Space-Division Packet SwitchIEEE Transactions on Communications, 1987
- A Broadband Packet Switch for Integrated TransportIEEE Journal on Selected Areas in Communications, 1987
- The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet SwitchingIEEE Journal on Selected Areas in Communications, 1987
- The Single Server Queue with Periodic Arrival Process and Deterministic Service TimesIEEE Transactions on Communications, 1979