Implementation of iterative networks with CMOS differential logic
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 23 (4), 1013-1017
- https://doi.org/10.1109/4.354
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A safe single-phase clocking scheme for CMOS circuitsIEEE Journal of Solid-State Circuits, 1988
- Design procedures for differential cascode voltage switch circuitsIEEE Journal of Solid-State Circuits, 1986
- Sample-set differential logic (SSDL) for complex high-speed VLSIIEEE Journal of Solid-State Circuits, 1986
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982
- Iterative Arrays ror Radix ConversionIEEE Transactions on Computers, 1971
- Testing for faults in combinational cellular logic arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1967