A 2 Gb/s Throughput GaAs Digital Time Switch LSI Using LSCFL

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/mcs.1985.1113649

Abstract

A GaAs four channel digital time switch having a 2.0 Gb/s throughput is developed. Low Power Source Coupled FET Logic (LSCFL) and 0.55 µm gate length buried p-layer SAINT-FETs are applied. The switch includes 1176 devices (FETs, diodes, and resistors). The 75 % fabrication yield is attained using dislocation free wafers.

Keywords

This publication has 4 references indexed in Scilit:

Below 10 ps/gate operation with buried p-layer SAINT FETs
Electronics Letters, 1984
Direct observation of dislocation effects on threshold voltage of a GaAs field-effect transistor
Applied Physics Letters, 1983
High-speed GaAs SCFL monolithic integrated decision circuit for Gbit/s optical repeaters
Electronics Letters, 1983
A GaAs MSI word generator operating at 5 Gbits/s data rate
IEEE Transactions on Electron Devices, 1982

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