A Simple Technique for Improving the Pull-in Capability of Phase-Lock Loops
- 1 March 1965
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Space Electronics and Telemetry
- Vol. SET-11 (1), 40-46
- https://doi.org/10.1109/TSET.1965.5009635
Abstract
This paper presents a simple technique for improving the pull-in capability of phase-lock loops. This technique, called derived rate rejection or DRR, differs from those which use an external AFC loop in simplicity of implementation and design rationale, although the end result is the same. If, as is usually the case, a coherent detector accompanies the phase-lock loop, the implementation of the DRR technique requires only the addition of a switch. The switching logic results from a superficial consideration of the nonlinear equation for the phase-lock loop and its solution in the phase plane. The switch does not affect the normal behavior of the loop after lock has been attained. Results of computer studies show the improvement realizable for the following configurations: 1) Proportional-plus-integral control. 2) Proportional-plus-imperfect integral control. For an initial frequency error of five times the linearized phase lock-loop natural frequency, the improvement in pull-in time is a factor of two. For an initial frequency error of ten times the phase-lock loop natural frequency, the improvement in pull-in time is a factor of ten.Keywords
This publication has 2 references indexed in Scilit:
- Phase-Lock Loop Frequency Acquisition StudyIRE Transactions on Space Electronics and Telemetry, 1962
- Design and performance of phase-lock circuits capable of near-optimum performance over a wide range of input signal and noise levelsIRE Transactions on Information Theory, 1955