Load-Sharing Core Switches Based on Block Designs

Abstract

Designs for load-sharing zero-noise core switches have been proposed by Constantine, Marcus, and Chien. Blachman class has proposed a core memory wiring plan which with modification can be converted to a load-sharing zero-noise switch. An examination of these switch plans shows that they have a common relationship to a class of mathematical structures known to mathematicians and statisticians as balanced incomplete block designs. This relationship is formulated, and it is then shown that all balanced incomplete block designs lead to load-sharing zero-noise switches. Three methods of forming the winding matrix for a switch are given, and expressions for the load-sharing factor, set bias, and reset bias in terms of the balanced incomplete block design parameters are derived for each switch type. Similarly, partially balanced incomplete block designs are shown to lead to low-noise load-sharing switches. Switch operation under fault conditions is briefly discussed. Most of the known load-sharing core switch types can be viewed as based on either balanced or partially balanced incomplete block designs. A review of the available block designs indicates that a number of new switches can be based on these designs. A modification of a distributed memory model proposed by C. Rosen is discussed. With wiring plans based on block designs, it appears possible to construct very-large-capacity memory units which are relatively insensitive to wiring errors.