The future of wires
Top Cited Papers
- 1 April 2001
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 89 (4), 490-504
- https://doi.org/10.1109/5.920580
Abstract
Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.Keywords
This publication has 30 references indexed in Scilit:
- 100 nm gate length high performance/low power CMOS transistor structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An efficient inductance modeling for on-chip interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Highly robust ultra-thin gate dielectric for giga scale technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Stacked gate dielectrics with TaO for future CMOS technologiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1 GHz Alpha microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Rationale and challenges for optical interconnects to electronic chipsProceedings of the IEEE, 2000
- VLSI architecture: past, present, and futurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1999
- Inductance on silicon for sub-micron CMOS VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Power distribution techniques for VLSI circuitsIEEE Journal of Solid-State Circuits, 1986