A design for an optical general purpose digital computer is presented. The basic approach involves decomposing the structure of a classical finite state machine into a logic unit, an interconnection array, and a latching unit. The logic unit is implemented with an optical NOR gate array. The NOR gate array involves projecting several binary images on a common surface, inverting, and thresholding the intensity of the result. Each pixel thus functions as a NOR gate. This NOR gate array is sufficient to establish a complete logical set. The interconnect array can be implemented with a hologram or conventional optics. Each pixel (x,y) is imaged to pixel (x,y-1), pixel (x+1,y-1), and pixel (x-2,y-1) on each cycle. This interconnection pattern is sufficient to establish a complete non-planar connective set. The latching unit serves as a memory. A delay is used as a memory in much the same manner as it was in earlier computers (mercury delay lines, CRT storage, etc.). The processor is programmed by customizing the interconnect pattern. This can be accomplished by tying the input of various optical NOR gates "high" with a customizing binary input image. This design illustrates how the parallelism of optics can be used to overcome the Von Neumann bottleneck which throttles the throughput of current computers.