Integrating the timing analysis of pipelining and instruction caching
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 288-297
- https://doi.org/10.1109/real.1995.495218
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- A retargetable technique for predicting execution timePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Program representation and translation for predictable real-time systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast instruction cache analysis via static cache simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Avoiding conditional branches by code replicationPublished by Association for Computing Machinery (ACM) ,1995
- Supporting user-friendly analysis of timing constraintsACM SIGPLAN Notices, 1995
- Efficient on-the-fly analysis of program behavior and static cache simulationLecture Notes in Computer Science, 1994
- Bounding worst-case instruction cache performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1994
- Calculating the maximum execution time of real-time programsReal-Time Systems, 1989
- Reasoning about time in higher-level language softwareIEEE Transactions on Software Engineering, 1989
- A portable global optimizer and linkerPublished by Association for Computing Machinery (ACM) ,1988