Informed device design and gain-speed trade-off for self-aligned polysilicon-emitter transistors
- 31 July 1988
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 31 (7), 1139-1150
- https://doi.org/10.1016/0038-1101(88)90273-0
Abstract
No abstract availableKeywords
This publication has 18 references indexed in Scilit:
- Numerical simulation of temperature-dependent minority-hole transport in n+ silicon emittersSolid-State Electronics, 1986
- Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistorsIEEE Transactions on Electron Devices, 1986
- Study of delay times contributing to the ftof bipolar transistorsIEEE Electron Device Letters, 1986
- An investigation of the tradeoff between enhanced gain and base doping in polysilicon emitter bipolar transistorsIEEE Transactions on Electron Devices, 1985
- Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistorsIEEE Electron Device Letters, 1985
- Self-aligned transistors with polysilicon emitters for bipolar VLSIIEEE Transactions on Electron Devices, 1985
- Comparison of experimental and theoretical results on polysilicon emitter bipolar transistorsIEEE Transactions on Electron Devices, 1984
- Effective recombination velocity of polysilicon contacts for bipolar transistorsElectronics Letters, 1984
- Effect of emitter contact on current gain of silicon bipolar devicesIEEE Transactions on Electron Devices, 1980
- Volt-current characteristics for tunneling through insulating filmsJournal of Physics and Chemistry of Solids, 1962