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A precision trim technique for monolithic analog circuits
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A precision trim technique for monolithic analog circuits
A precision trim technique for monolithic analog circuits
GE
G. Erdi
G. Erdi
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1 January 1975
conference paper
Published by
Institute of Electrical and Electronics Engineers (IEEE)
Vol. XVIII
,
192-193
https://doi.org/10.1109/isscc.1975.1155393
Abstract
A precision shortable diode trim design applied at the wafer test phase, will be described, citing adjustment of op-amp offset to 2.5 μV and drifts to less than 0.6 μV/°C.
Keywords
ANALOG CIRCUITS
OPERATIONAL AMPLIFIERS
VOLTAGE
ZINC
TEMPERATURE
CIRCUIT TESTING
SEMICONDUCTOR DIODES
INSTRUMENTS
CIRCUIT NOISE
EQUIVALENT CIRCUITS
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Cited by 6 articles