It is no longer sufficient for foundries to provide only process technology qualification data (for example, device hot carrier, TDDB, BTI, interconnect EM, SM etc.) to the fabless companies as it has been done traditionally. At the nanometer scale, process variations (die to die & within die) coupled with shrinking reliability margins have significantly reduced the design space while circuit designs become increasingly complicated. Foundries need to provide detailed reliability information to enable process-variability & reliability-aware designs that allow the fabless users to leverage the benefits of the advanced technologies. The information is needed for all users and is critical to be available in the process development phase for early technology adaptors. Information should include detailed reliability design rules/tools in form of device/interconnect degradation models that incorporate statistical/process variations. These models/tools can help designers to identify and to mitigate circuit reliability risks in the early design phase. This paper addresses this shift of paradigm that allows fabless designs to keep pace with the rapidly changing nano scale technologies.