A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
- 1 November 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 27 (11), 1599-1607
- https://doi.org/10.1109/4.165341
Abstract
A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8- mu m CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency.Keywords
This publication has 5 references indexed in Scilit:
- A CMOS 100MHz MicroprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- An enhancement-mode MOS voltage-controlled linear resistor with large dynamic rangeIEEE Transactions on Circuits and Systems, 1990
- A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOSIEEE Journal of Solid-State Circuits, 1990
- A variable delay line PLL for CPU-coprocessor synchronizationIEEE Journal of Solid-State Circuits, 1988
- Charge-Pump Phase-Lock LoopsIEEE Transactions on Communications, 1980