Architecture and compiler enhancements for PA-RISC workstations
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A set of extensions to Hewlett-Packard's Precision RISC (reduced instruction set computer) Architecture is described. These extensions allow a higher level of floating-point performance and represent the first wave of enhancements to PA-RISC inspired by workstation requirements. The role of these architecture changes and the enhanced optimization capabilities of the PA-RISC compilers are reviewed with an emphasis on their impact on application performance. A discussion of compatibility with previous PA-RISC systems and HP's MC680*0-based workstations is also presented.<>Keywords
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