A One-Microsecond Adder Using One-Megacycle Circuitry

Abstract

An analysis of the functional representation of the carry digits in the addition process shows that the one-megacycle circuitry of SEAC and DYSEAC can be organized logically to permit the formation of many successive carries simultaneously. The Boolean expression for any carry digit Ck can be expanded so as to be an explicit function of only the input digits of orders k to k-p+1 and of the carry digit Ck-p. Certain factorizations can then be made to simplify these expressions so that all of them fall within the limitations on the gating complexity imposed by the circuitry. A parallel adder utilizing this principle is developed which is capable of adding two 53-bit numbers in one microsecond, with relatively few additional components over those required in a parallel adder of more conventional design.