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Differential pass transistor logic in CMOS technology
Home
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Differential pass transistor logic in CMOS technology
Differential pass transistor logic in CMOS technology
AS
A.S. Shubat
A.S. Shubat
JP
J.A. Pretorius
J.A. Pretorius
CS
C.A.T. Salama
C.A.T. Salama
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1 January 1986
journal article
Published by
Institution of Engineering and Technology (IET)
in
Electronics Letters
Vol. 22
(6)
,
294-295
https://doi.org/10.1049/el:19860200
Abstract
Differential pass transistor logic is described in the letter. This configuration results in better silicon area efficiency and higher speed of operation than conventional CMOS pass transistor logic.
Keywords
CLOCKED BUFFERS
SI AREA EFFICIENCY
CONFIGURATION
CMOS DIFFERENTIAL PASS TRANSISTOR LOGIC
OPERATION SPEED
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Cited by 6 articles