A buried channel/surface channel CMOS IC isolated by an implanted silicon dioxide layer

1 March 1982

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 29 (3), 459-461
https://doi.org/10.1109/T-ED.1982.20723

Abstract

The design and experimental results for a buried channel/ surface channel CMOS IC isolated by an implanted silicon dioxide layer are presented. A Poisson equation is used in proposing a threshold voltage model for a FET with metal-insulator-semiconductor-insulator-semiconductor (MISIS) structure. Good agreement between measured and calculated threshold voltage versus substrate voltage characteristics is obtained. The propagation delay for an inverter is 0.83 ns, which agrees with that from simulation.

Keywords

STRUCTURE
MODEL
SILICON
CMOS
SEMICONDUCTOR
IMPLANTED
BURIED
DIOXIDE
CHANNEL/SURFACE

Cited by 2 articles