Modeling of an ion-implanted silicon-gate depletion-mode IGFET

Abstract

A dc model is-presented for the ion-implemented silicon-gate depletion-mode IGFET from which the device terminal behavior can be determined. The device equations are derived based on the concept of a finite semiconductor capacitance in the channel region whereby the depth of the implanted channel is taken into account. The model parameter is shown to be easily measurable experimentally. The validity of the resulting model is demonstrated by showing good agreement between calculated and measured results obtained from fabricated devices, It is believed that this model lends itself well to the circuit design problem using depletion mode IGFET's.