A dual differential charge-coupled analog delay device
- 1 February 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 11 (1), 105-108
- https://doi.org/10.1109/JSSC.1976.1050683
Abstract
A dual differential charge-coupled analog device providing signal delays of 24 and 48 elements has been designed for sampled data analog signal processing applications. The aim of this design was to eliminate some of the disadvantages that have been associated with previous charge-coupled devices (CCD's). These include clock pickup, thermally generated d.c. offsets, and complex external control and amplification circuitry. The device has an input strobing circuit and an on-chip output amplifier. With a clock frequency of 8 kHz and a 400-mV r.m.s. input signal, the total harmonic distortion was below 0.2 percent and the signal-to-noise ratio was better than 70 dB with a 4-kHz bandwidth. The device gain was 6 dB and a gain variation of 0.2 dB was observed over a temperature range of 0 to 55/spl deg/C.Keywords
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