Transient analysis of multiple-input integrated digital structures

Abstract

This paper presents an insight into the transient performance and propagation delay of complex integrated multiple-input structures in relation to a large digital system, taking into account the intrinsic parameters associated with device geometry. Modeling is therefore performed at the gate level. A piecewise linear model is used for the various transient intervals and the analysis employs fixed time steps. Experimental observations give ample evidence of good agreement between the theoretical and computed results, for which various values of input rise and fall times and different values of fan-out, β0, and fTare used. An accurate appraisal of the storage time associated with the gate is thus possible. Detailed solutions determine the main factors that offer scope for improvement for the structure studied, and suggest means of optimizing the transient response using the derived analytical expressions.