A new flash-erase EEPROM cell with a sidewall select-gate on its source side
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 603-606
- https://doi.org/10.1109/iedm.1989.74353
Abstract
A novel flash-erase EEPROM (electrically erasable PROM) cell is described. It consists of a stacked-gate MOSFET with a sidewall select gate on the source side of the FET (SISOS cell). Three layers of polysilicon are used. The cell has a self-aligned structure which makes it possible to realize a small cell area of 4.0*3.5 mu m/sup 2/ with 1.0- mu m technology. It also has a select gate which prevents undesirable leakage current due to overerasing. The cell is programmed by channel hot electron injection at the source side and erased by Fowler-Nordheim tunneling of electrons from the floating gate to the drain. The programming by source-side injection makes it possible for the drain junction to be optimized independently of hot electron generation and for the erasure to be achieved with no degradation in programmability.Keywords
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