The Effect of Gate Oxide Thickness on the Radiation Hardness of Silicon-Gate CMOS

Abstract

Significant improvements have been made in the radiation hardness of silicon-gate CMOS by reducing the gate oxide thickness. The device studied is an 8-bit arithmetic logic unit designed with Sandia's Expanded Linear Array (ELA) standard cells. Devices with gate oxide thicknesses of 400, 570 (standard), and 700 A were fabricated. Irradiations were done at a dose rate of 2 × 106 rads (Si) per hour. N- and P-channel maximum threshold shifts were reduced by 0.3 and 1.2 volts, respectively, for the thinnest oxide. Between a linear and squared relationship is found for threshold shift versus thickness. The functional radiation hardness of the full integrated circuit was also measured. Maximum power supply current after irradiation was reduced by an order of magnitude for the thinnest oxide. The speed degradation of parts after 1 × 106 rads (Si) was reduced by 30 percent. Dose rate and annealing behavior at room temperature were also studied. A dose rate of 1 × 103 rads per hour results in no increase in power supply current. The speed change was similar to high dose rate plus anneal. Annealing after high dose rate (2 × 106 rads (Si) per hour) results in recovery of the N-channel threshold towards accumulation. Functionally, power supply current decreases and the parts slow down with time after irradiation. Thinning gate oxide of the silicon-gate CMOS results in better radiation hardness for all annealing studies as well.