Josephson integrated circuit process for scientific applications
- 1 March 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Magnetics
- Vol. 23 (2), 1484-1488
- https://doi.org/10.1109/tmag.1987.1065115
Abstract
We have developed and are regularly practicing a seven mask-level Josephson integrated circuit fabrication process tailored to dc SQUID requirements and intended for SQUID studies and other scientific applications of Josephson technology. The process incorporates low capacitance Nb/Nb2O5/PbAuIn edge junctions, PdAu shunt resistors, and a wiring pitch of 5 μm for the SQUID input coil level (which is PbAuIn). The junctions can be made as small as 2μm by 0.3μm, with a capacitance (including parasitics) of ∼0.14 pF. This process yields stable and reliable junctions and integrated circuits.Keywords
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