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Hierarchical top-down layout design method for VLSI chip
Home
Publications
Hierarchical top-down layout design method for VLSI chip
Hierarchical top-down layout design method for VLSI chip
TA
Tohru Adachi
Tohru Adachi
HK
Hitoshi Kitazawa
Hitoshi Kitazawa
MN
Mitsuyoshi Nagatani
Mitsuyoshi Nagatani
TS
Tsuneta Sudo
Tsuneta Sudo
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1 January 1982
conference paper
Published by
Association for Computing Machinery (ACM)
https://doi.org/10.1145/800263.809291
Abstract
No abstract available
Cited by 3 articles