A low-voltage BiMOS op amp
- 1 December 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 16 (6), 661-668
- https://doi.org/10.1109/jssc.1981.1051659
Abstract
Describes the development of a threshold implanted BiMOS amplifier IC optimized for 2-5 V operation at a supply current of 300 /spl mu/A. A nonlinear operational transconductance amplifier (OTA) buffer having on-chip feedback provides a low-impedance rail-to-rail output, and a bulk-modulated PMOS input pair extends the common-mode range. Protective-network bootstrapping makes possible subpicoampere input-bias currents below 85/spl deg/C, and improved offset stability is achieved by the choice of threshold-level stage currents. Amplifier design is straightforward and readily applied from `micropower' to `broad-band' operating ranges. The combination of these features has produced a unique high-performance integrated circuit.Keywords
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