Radiation Failure Modes in CMOS Integrated Circuits
- 1 January 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 20 (6), 300-306
- https://doi.org/10.1109/tns.1973.4327411
Abstract
The radiation sensitivity of commercial and laboratory CMOS processes has been investigated. Failure levels for CMOS circuits have been related to transistor threshold voltage shifts and typical inverter failure modes. CMOS inverter characteristics have been measured as a function of the ionizing radiation exposure for devices fabricated by 10 different manufacturers and representing a total of 15 different processes. By selecting certain processes, CMOS circuits can be obtained which will operate after exposure to an ionizing radiation dose greater than 106 rads (Si).Keywords
This publication has 6 references indexed in Scilit:
- Determining the Energy Distribution of Pulse-Radiation-Induced Charge in MOS Structures from Rapid Annealing MeasurementsIEEE Transactions on Nuclear Science, 1972
- The Effects of Ionizing Radiation on Various CMOS Integrated Circuit StructuresIEEE Transactions on Nuclear Science, 1972
- Model for Radiation-Induced Charge Trapping and Annealing in the Oxide Layer of MOS DevicesJournal of Applied Physics, 1969
- Radiation-induced space-charge buildup in MOS structuresIEEE Transactions on Electron Devices, 1967
- Radiation-induced increase in surface recombination velocity of thermally oxidized silicon structuresProceedings of the IEEE, 1966
- An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodesSolid-State Electronics, 1962