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A 32b CMOS microprocessor with on-chip instruction and data caching and memory management
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Publications
A 32b CMOS microprocessor with on-chip instruction and data caching and memory management
A 32b CMOS microprocessor with on-chip instruction and data caching and memory management
DA
D. Archer
D. Archer
DD
D. Deverell
D. Deverell
FF
F. Fox
F. Fox
PG
P. Gronowski
P. Gronowski
AJ
A. Jain
A. Jain
ML
M. Leary
M. Leary
AO
A. Olesin
A. Olesin
SP
S. Persels
S. Persels
PR
P. Rubinfeld
P. Rubinfeld
DS
D. Schumacher
D. Schumacher
BS
B. Supnik
B. Supnik
TT
T. Thrush
T. Thrush
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23 March 2005
conference paper
Published by
Institute of Electrical and Electronics Engineers (IEEE)
p.
32-33
https://doi.org/10.1109/isscc.1987.1157147
Abstract
A processor implemented with 180K transistors in 2μm CMOS technology will be presented. The chip size is 9.7mm × 9.4mm, and the instruction set is compatible with a minicomputer.
Keywords
MICROPROCESSORS
MEMORY MANAGEMENT
REGISTERS
PREFETCHING
LOGIC
CLOCKS
SIGNAL GENERATORS
PROTECTION
DECODING
PULSE GENERATION
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Open Access
Cited by 6 articles