A 32b CMOS microprocessor with on-chip instruction and data caching and memory management

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 32-33
https://doi.org/10.1109/isscc.1987.1157147

Abstract

A processor implemented with 180K transistors in 2μm CMOS technology will be presented. The chip size is 9.7mm × 9.4mm, and the instruction set is compatible with a minicomputer.

Keywords

MICROPROCESSORS
MEMORY MANAGEMENT
REGISTERS
PREFETCHING
LOGIC
CLOCKS
SIGNAL GENERATORS
PROTECTION
DECODING
PULSE GENERATION

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