Graph-Optimization Techniques for IC Layout and Compaction
- 1 January 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 3 (1), 12-20
- https://doi.org/10.1109/tcad.1984.1270052
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- The complexity of compacting hierarchically specified layouts of integrated circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- SLIP: symbolic layout of integrated circuits with compactionComputer-Aided Design, 1978
- A sequential approach to the extraction of shape featuresComputer Graphics and Image Processing, 1977