Abstract
A FDCT (fast discrete cosine transform) processor is designed to have throughput rates consistent with high speed, (real time) processing of standard National Television Systems Committee (NTSC) color television signal sampled at 3fsc = 10.7 MHz where fsc is the color subcarrier frequency. This is achieved by using a highly modular structure in a pipeline configuration. The development phase includes the selection of a suitable algorithm and the utilization of important features of the algorithm for hardware implementation. Since the prototype is used for research purposes, provisions are made for versatility of the control and selectabilifty of , the processing accuracy. The FDCT processor is capable of processing 4- or 8- or 16- point input segments and can also be used as a part of a larger system which processes a 32-point input segment. With minor modifications, the algorithm and the basic hardware design can be used for the fast inverse DCT (FIDCT) processor.

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