Graphical Analysis of a Digital Phase-Locked Loop

Abstract

Under the assumption of negligible quantization error effect and no noise, a nonuniform sampling first-order digital phase-locked loop (DPLL) is analyzed by a graphical method which displays limit cycles and the cycle slipping phenomenon. The analysis suggests an upper bound to the model gain and, consequently, to the pull-in range. Moreover, this method enables one to obtain a closed-form expression of the acquisition time, accurate enough for the cases of practical interest.