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A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI
Home
Publications
A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI
A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI
HS
H. Shichijo
H. Shichijo
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1 January 1981
proceedings article
Published by
Institute of Electrical and Electronics Engineers (IEEE)
https://doi.org/10.1109/iedm.1981.190046
Abstract
No abstract available
Keywords
VERY LARGE SCALE INTEGRATION
SERIES RESISTANCE
THRESHOLD VOLTAGE
ELECTRIC RESISTANCE
SCALABILITY
CONTACT RESISTANCE
PARASITIC CAPACITANCE
DOPING
DEGRADATION
Cited by 8 articles