A Heuristic Algorithm for the Testing of Asynchronous Circuits
- 1 June 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-20 (6), 639-647
- https://doi.org/10.1109/t-c.1971.223315
Abstract
This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given.Keywords
This publication has 5 references indexed in Scilit:
- Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic CircuitsIEEE Transactions on Electronic Computers, 1967
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966
- Hazard Detection in Combinational and Sequential Switching CircuitsIBM Journal of Research and Development, 1965
- Design of Serviceability Features for the IBM System/360IBM Journal of Research and Development, 1964
- The Diagnosis of Asynchronous Sequential Switching SystemsIEEE Transactions on Electronic Computers, 1962