A programmable CCD tapped delay line, useful in radar and communications signal processors, is described. The 64-stage CCD, tapped at each stage, has been operated as a binary-weighted analog correlator, and as a bandpass filter. The CCD is a shallow, buried, n-channel device while the on-chip logic required for reference code input and storage is NMOS. Test results indicate near-theoretical peak-to-sidelobe ratio for 64-bit codes, good linearity, and high-speed operation (in excess of 15 MHz). Differential subtraction of summed signal currents on-chip has been demonstrated.