Error Correction in High-Speed Arithmetic
- 1 May 1972
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-21 (5), 433-438
- https://doi.org/10.1109/T-C.1972.223538
Abstract
In high-speed multipliers, multiplication is activated by processing a group of bits in parallel. As a result, any defects in circuitry produce possible errors in positions that are separated by fixed periods. A class of codes for the correction of such iterative error patterns resulting from a single fault is presented in this paper. A decoding algorithm together with a simple implementation scheme is also discussed.Keywords
This publication has 7 references indexed in Scilit:
- Discussion on "Arithmetic codes with large distance" by Mandelbaum, D.IEEE Transactions on Information Theory, 1968
- Calculation of Mean Shift for a Binary Multiplier Using 2, 3, or 4 Bits at a TimeIEEE Transactions on Electronic Computers, 1967
- Arithmetic codes with large distanceIEEE Transactions on Information Theory, 1967
- Arithmetic Error Detecting Codes for Communications Links Involving ComputersIEEE Transactions on Communications, 1965
- On linear residue codes for burst-error correctionIEEE Transactions on Information Theory, 1964
- Prime-residue error correcting codes (Corresp.)IEEE Transactions on Information Theory, 1964
- High-Speed Arithmetic in Binary ComputersProceedings of the IRE, 1961