Synthesis and Optimization of Multilevel Logic under Timing Constraints
- 1 October 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 5 (4), 582-596
- https://doi.org/10.1109/tcad.1986.1270229
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Synthesis and Optimization of Multilevel Logic under Timing ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- A Rule-Based System for Optimizing Combinational LogicIEEE Design & Test of Computers, 1985
- LSS: A system for production logic synthesisIBM Journal of Research and Development, 1984
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- Multiple Constrained Folding of Programmable Logic Arrays: Theory and ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- An Algorithm for Optimal PLA FoldingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982