A PLL clock generator with 5 to 110 MHz lock range for microprocessors

Abstract

The authors describe a phase-locked-loop (PLL)-based deskewed clock generator that is fully integrated with a microprocessor and achieves a skew of less than 0.1 ns with peak-to-peak jitter of 0.45 ns using an 0.8- mu m CMOS technology. The block diagram of the deskewed clock generator is shown along with the measured schmoo diagram of the PLL clock generator functionality frequency versus supply voltage.