A Simulation Study of Decoupled Architecture Computers
- 1 August 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-35 (8), 692-702
- https://doi.org/10.1109/tc.1986.1676820
Abstract
Decoupled architectures achieve high scalar performance by cleanly splitting instruction processing into memory access and execution tasks. Several decoupled architectures have been proposed, and they all have two characteristics in common: 1) they have two separate sets of instructions, one for accessing memory and one for performing function execution. 2) The memory accessing task and the execution task communicate via architectural queues.Keywords
This publication has 9 references indexed in Scilit:
- Decoupled access/execute computer architecturesACM Transactions on Computer Systems, 1984
- Instruction Issue Logic in Pipelined SupercomputersIEEE Transactions on Computers, 1984
- Decoupled access/execute computer architecturesACM SIGARCH Computer Architecture News, 1982
- Architecture of a Programmable Digital Signal ProcessorIEEE Transactions on Computers, 1982
- Functionally Parallel Architecture for Array ProcessorsComputer, 1981
- The CRAY-1 computer systemCommunications of the ACM, 1978
- Information content of CPU memory referencing behaviorPublished by Association for Computing Machinery (ACM) ,1977
- The IBM System/360 Model 91: Machine Philosophy and Instruction-HandlingIBM Journal of Research and Development, 1967
- Very high-speed computing systemsProceedings of the IEEE, 1966