Topological Optimization of Multiple-Level Array Logic
- 1 November 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (6), 915-941
- https://doi.org/10.1109/tcad.1987.1270335
Abstract
No abstract availableThis publication has 27 references indexed in Scilit:
- PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex SystemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2010
- Chameleon: A New Multi-Layer Channel RouterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Convergence of an annealing algorithmMathematical Programming, 1986
- Optimization by Simulated AnnealingScience, 1983
- Pictures with Parentheses: Combining Graphics and Procedures in a VLSI Layout ToolPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Design aids for VLSI: The Berkeley perspectiveIEEE Transactions on Circuits and Systems, 1981
- One-dimensional logic gate assignment and interval graphsIEEE Transactions on Circuits and Systems, 1979
- The CMU Design Automation System - An Example of Automated Data Path DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- MINI: A Heuristic Approach for Logic MinimizationIBM Journal of Research and Development, 1974
- An Efficient Heuristic Procedure for Partitioning GraphsBell System Technical Journal, 1970