Evanescent-mode analysis of short-channel effects in fully depleted SOI and related MOSFETs

Abstract

Fully depleted SOI (FDSOI) and double-gate (DG) structures offer significant improvement in long-channel subthreshold swing over bulk devices, which are heavily doped to reduce short-channel effects (SCEs) such as threshold voltage (V/sub T/) roll-off and drain-induced barrier lowering (DIBL). Using idealized devices, we argue that previous SCE analyses fail to solve the electrostatics problem, and scale incorrectly with device dimensions. Although FDSOI devices can be as much as three (=/spl epsiv//sub Si///spl epsiv//sub oxide/) times shorter than bulk devices with identical SCE, our analysis indicates that this requires both buried oxide and silicon thicknesses to be 30-60% of the effective gate length L/sub eff/, a daunting prospect for L/sub eff/<100 nm.