Finite precision error analysis of neural network electronic hardware implementations

Abstract

The high speed desired in the implementation of many neural network algorithms, such as backpropagation learning in multilayer perceptrons (MLPs), may be attained through the use of finite-precision hardware. This finite precision hardware, however, is prone to errors. A method of theoretically deriving and statistically evaluating this error is presented. This could be used as a guide to the details of hardware design and algorithm implementation. The authors describe the derivation of the techniques involved, as well as the details of the backpropagation example. The intent is to provide a general framework by which most neural network algorithms under any set of hardware constraints may be evaluated.