Radiation Hardened CMOS/SOS
- 1 December 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 22 (6), 2181-2184
- https://doi.org/10.1109/tns.1975.4328101
Abstract
This paper reports the results of experiments designed to optimize the total dose ionizing radiation hardness of CMOS/SOS devices. Type 4007 inverter circuits were fabricated with variations in the process, including wet versus dry gate oxidation. Tolerable values (e. g. < l#x003BC;A per mil of channel width) of post-radiation n-channel back leakage were obtained only with wet oxides. Threshold shifts of ≤1V for the n-channel devices and ≤2V for the p-channel devices were obtained after 106 rads (Si) on the best devices fabricated.Keywords
This publication has 4 references indexed in Scilit:
- Effects of HCL gettering, CR doping and AL+ implantation on hardened SiO2IEEE Transactions on Nuclear Science, 1974
- Radiation induced leakage current in N-channel SOS transistorsIEEE Transactions on Nuclear Science, 1974
- Radiation hardening of CMOS/SOS integrated circuitsIEEE Transactions on Nuclear Science, 1974
- Radiation induced charge trapping at the silicon sapphire substrate interfaceIEEE Transactions on Nuclear Science, 1974