Neural networks using analog multipliers
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 499-502
- https://doi.org/10.1109/iscas.1988.14973
Abstract
A neural network implementation using MOSFET analog multipliers to construct weighted sums is described. This scheme permits asynchronous, analog operation of Hopfield style networks with fully programmable binary weights. This approach avoids the use of large-valued resistors which waste chip area or require special processing. Using this approach, analog neurons can be constructed in as few as 2+2 K transistors per Kb connection weight. An analytical model for the analog multipliers has been derived. This model has been used to stimulate a complete neural network for the traveling salesman problem.> Author(s) Paulos, J.J. Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA Hollis, P.W.Keywords
This publication has 3 references indexed in Scilit:
- VLSI implementation of a neural network memory with several hundreds of neuronsAIP Conference Proceedings, 1986
- VLSI architectures for implementation of neural networksAIP Conference Proceedings, 1986
- Neural networks and physical systems with emergent collective computational abilities.Proceedings of the National Academy of Sciences, 1982